Back to my Diversity SDR project

4 Channel Diversity Hardware

Vivado Block Diagram

I finally took some time out from DATV-Express to work on my SDR.
The hardware consists of a Digilent Zedboard (Zynq 7020) an Analog Devices
interposer board (which required a slight modification) and an Analog Devices
AD9253 ADC evaluation board. The Zedboard was bought used from a
seller on eBay so I paid about half the retail price but as I didn't get the
Xilinx licence I am using the free webpack version.

The OS I plan to run is FreeRTOS I think I have the FPGA code just about
finished and am now starting on the C code for the ARM part of the Zynq.
This will primarily just be taking data DMAed from the PL (FPGA) fabric
and sending it out over Ethernet. 

The board is currently running a demo program that uses the lwIP
stack which I plan to use as a framework for my own application.
I am calling it Diversity4SDR (because it has 4 channels).

The AD9253 is a 4 channel 125 MS/s 14 bit ADC. The FPGA code which uses
mainly free Xilinx AXI4 IP blocks decimates the 125 MS/s into 4x 1MS/s
channels so they will fit over 1Gbit Ethernet.

As SDRs are pretty simple to do I am using this as a training exercise to
get up to speed with Xilinx Vivado . Eventually I plan to use Vivado
to implement a DPD system.

What has spurred me on to get back to this is the excellent work done by
Pavel Demin examining what he has done has help tremendously with the
FPGA code.

Now you know why I seldom ever get on the radio.