some time and finally I have the bits to make one.
To the left is a development board for an AD9253 quad 125 MS/sec 14 bit ADC.
The middle is an interposer board to adapt between the connectors used on the
ADC board and the FMC connector on the FPGA board. This board requires a
minor modification (to do with the framing clock signal). On the right is a Xilinx
SP601 evaluation board. The plan is to have a simple bit of code on the FPGA
to stitch together all the ICs, frame the data and send it over 1Gbit Ethernet to the
P.C for processing. The limiting factor is the 1Gbit Ethernet (of course).
Using Xilinx FPGA tools is new to me, (in the past I have used Altera) but I have
managed to write and deploy a simple program to the board. Xilinx have a different
way of doing things but the principals are the same.
Of course the FPGA board wants 5V and the AD9253 board 6V.
It will only be a 4 channel diversity receiver but that is a start but once I have verified
that it works at HF I plan to add VHF / UHF / SHF down converters to it.