|ARM CPU configuration|
|System block diagram|
|Random data being transmitted|
After a lot of studying I have managed to make some progress on my next gen DATV
project. This is all relatively new technology for me so it has taken a lot longer than
I had hoped. Some of the time was wasted by the rather poor documentation of
the sample clock generation chip on the Zipper board but I think I have it correct now.
I have a working PetaLinux installation, GPIO, I2C and SPI control of the devices
on the Zipper and MyriadRF boards.
Interfacing of my custom IP logic in the FPGA to the ARM device uses generic io
The IP in the PL (FPGA) is currently very simple but will be expanded to provide
many more advanced features. It takes IQ samples from the host and sends them
to the MyriadRF board for transmission. The ultimate aim will be to add Digital
Pre-Distortion code in the PL logic to correct for non linearities in the transmit
chain. On transmit the receive channel will monitor the transmitter output and
carry out the required real time maths. On the receive obviously the receive channel
will be used for demodulation of the received signal.
In the first phase I am simply going to use a PC based program like GNURadio
or DATV-Express to generate samples that will be sent to the Zedboard via
Gigabit Ethernet. I will probably post again when I have something sensible to