Wednesday, 4 May 2016

SDR part 2

Work on the SDR continues but it is proving to be quite complicated to
get to work. I am currently working on the ADC interface to the software.

Originally I tried to implement it with plain logic but that did not prove fast
enough. I am now doing the job properly using ISERDESE2 and IDELAYE2

The ISERDESE2 block does the serial to parallel conversion but
it is necessary to use IDELAYE2 blocks to delay the sample clocks so they
are centred at the eye of the symbol. The reason for this is the time uncertainty due
to a delays caused by buffering and routing of the high speed data clock.

The software has to go through a training sequence where it moves the sample
point to find the bit transition points. This is controlled by a state machine.
An ISERDESE2 block is used in the clock sync subsystem were it
correlates the clock against itself to find the optimum sample point. More
ISERDESEs are used for the actual de-serialisation of the data lanes.
There are 2 data lanes per channel and four channels.
The channels operate at 500 MHz (4 x 125 MHz). Data is read on both
the rising and the falling edges of the data clock.
Because of the delay added by the IDELAYE2 to the data clock it is also
necessary to use bit slipping to regain frame alignment of the bitstream.

The good news is that according to the Xilinx data sheet what I am trying to do
is well within the abilities of  my Zynq, it is just going to take a bit longer than
I had hoped.

On the bright side this exercise is forcing me to finally learn how to write code
for Zynq based systems as I have had to use so many aspects of the device.

I have FreeRTOS working as the embedded OS, DMA from PL to PS working.
SPI comms to the ADC working and of course TCP/IP/Ethernet using
lwip for comms working.

I have included an image of the prototype system talking to SDR# using the
NetSdr protocol used by RFSpace just to prove I have been busy.

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