I have decided to change the buffering in the FPGA code.
I am moving to FX2 synchronous slave mode and am reading
the samples into a FIFO within the FPGA then reading the
samples out of the FIFO as required by the DACs. Of course
this means a complete change to the FPGA software.
My O.U maths course MST209 starts in a few days time so
I will have to scale back the amount of work I am doing on
the Express project. Hopefully this year I can plan my time
more efficiently.
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