No I have not but the modulator chip draws about 2 watts which is a bit disappointing.
The range I quoted was the frequency range over which I managed to get it to lock. The low end is due to the size of the dividers in the chip and the high end is the VCOs internal to the chip. The VCOs actually operate at twice the output frequency so it is actually running at 4.8 GHz.
I noticed from the data sheet that the ADRF6755 is a thirsty little guy. 4.8 is asking a lot considering that the highest their other PLL/VCO's go is 4GHZ. Mixing up to 9cm is not that big a deal, have to do it anyway to get to 3cm.
I plan using a 9 GHz Stellex YIG and SMA mixer for 10 GHz. For the PA I am going to use a 2W EYAL GAL unit http://www.rfdesign.co.uk/microwave/Content/Eyal-Gal-10GHz-Transceiver.pdf
Hi, On the hardware side we are in the process of sorting out the various requirements for CE certification. On the software side I am about about to start testing some new FPGA code. I am hoping to have that done by the end of the month. There will be one final correction to the board layout before full manufacturing can start.
Hi Mike, the answer is no. FM TV uses a huge amount of bandwidth and you have to sample at twice the bandwidth minimum. There are a number of ways you can then process the signal, for example the dual differentiator algorithm, the arctangent detector or a phase lock loop. They are all computationally expensive. It is just so much easier to do it in analogue.
Very Interesting Charles the explanation Keep up the good work
ReplyDeleteCharles,
ReplyDeleteInformative video, thanks.
The 5.5 V reg appears to be a switcher with the others linear, have you measured the native current draw at 12 Volts?
Very broad RF output range, have you pushed it to see how much above 2480 it will go?
Looking forward to getting one.
Mike
No I have not but the modulator chip draws about 2 watts which is a bit disappointing.
ReplyDeleteThe range I quoted was the frequency range over which I managed to get it to lock. The low end is due to the size of the dividers in the chip and the high end is the VCOs internal to the chip. The VCOs actually operate at twice the output frequency so it is actually running at 4.8 GHz.
I noticed from the data sheet that the ADRF6755 is a thirsty little guy. 4.8 is asking a lot considering that the highest their other PLL/VCO's go is 4GHZ. Mixing up to 9cm is not that big a deal, have to do it anyway to get to 3cm.
DeleteI plan using a 9 GHz Stellex YIG and SMA mixer for 10 GHz.
DeleteFor the PA I am going to use a 2W EYAL GAL unit
http://www.rfdesign.co.uk/microwave/Content/Eyal-Gal-10GHz-Transceiver.pdf
How is things Going Charles on the Datv Express Front.
ReplyDeleteHi, On the hardware side we are in the process of sorting out the various requirements for CE certification. On the software side I am about about to start testing some new FPGA code. I am hoping to have that done by the end of the month. There will be one final correction to the board layout before full manufacturing can start.
ReplyDelete- Charles
Charles,
ReplyDeleteI still have a certain fondness for wideband FM ATV and was wondering if there might be a low cost embedded DSP solution for FM demod?
Mike
Hi Mike, the answer is no. FM TV uses a huge amount of bandwidth and you have to sample at twice the bandwidth minimum. There are a number of ways you can then process the signal, for example the dual differentiator algorithm, the arctangent detector or a phase lock loop. They are all computationally expensive. It is just so much easier to do it in analogue.
DeleteThanks for the explanation.
ReplyDelete