Latest update on the DATV-Express project

It is now looking like the board will be available in early January at the latest.
We will have a small quantity of production quality boards in mid October,
if they are fine and I am sure they will be we will then decide on the size of
the initial batch and that will determine the cost. We will also be able to give
a more definite release date. This project is being funded by team members.
No Kick-starting for us!

On the hardware side we have managed to clean up the power supply to the
MMIC this means the output will be cleaner than the board I am currently
using.

On the software side I have added extra interpolation rates to the software
which has meant that I have been able to transmit a 8 MHz channel DVB-T
signal using the board which I was unable to do before. I am also thinking
of adding a further x16 interpolation rate to allow alias free operation below
1 MSymbol/s. At the moment you need external filtering if you operate
below 1.5 MSymbols/s as there is an alias about 8 MHz away. This x16 rate
would also be useful, if sometime in the future I decide to add SSB/CW
generation to the board or allow the board to operate with GNURadio.
Adding the extra interpolation rate will use up a lot of extra resources.
The FPGA is currently 30% full. However there is not much more to add
so it will all fit in.

I am hoping that once the board is available people will be inspired to
develop new applications for it.  What will make or break the project is how
many other people get involved. The project is fairly unique in that it is a
transmit only board. There are plenty of SDR receivers and transceivers about
but not many transmit only boards. We decided to do it that way as Digital TV
receiver modules are very cheap and it would add considerable cost to the board
if we added a receive capability. Using an ASIC/custom chip to demodulate the
digital TV signal is a much better way to go as the latest generation of  Digital
TV signals use processor intensive FEC decoders (Low Density Parity Check
codes and Belief Propagation Decoding) which would not be cost effective to
implement on either the FPGA or in the host CPU.

We have also been asked why we haven't included an MPEG2 video encoder on
the board. The answer is simple it would have added considerably to the cost and
also made the board obsolete. We want it to also work with H.264 (MPEG4) and
eventually H.265 (HEVC) and whatever comes afterwards.